1. Field of the Invention
The present invention generally related to shielded clock trees and more particularly to a shielded clock tree that includes switches in the ground wiring that connects the shields to ground, where the switches are adapted to connect the shielding to ground during non-test operations and to selectively disconnect the shielding from ground during test operations.
2. Description of the Related Art
Clock shielding is used to electrically isolate major portions of a clock tree within an integrated circuit structure. In general, the shielding is used on all portions of the clock tree up to the clock splitters. The shielding is generally implemented as grounded, minimum size, and minimum spaced wires on either side of the clock running segment, as shown in FIG. 1. More specifically, FIG. 1 illustrates a clock buffer (SCB) 100 that provides a main clock signal along the main clock signal lines 102. This main clock signal is distributed along the main clock signal lines 102 to secondary structured clock buffers 104 which provide the secondary clock signals. The secondary clock signals are transmitted along secondary clock signal lines 106 to clock splitters 108. The shields 110 are adjacent and parallel to the main clock signal lines 102 and secondary clock signal lines 106, and are conventionally grounded as shown in FIG. 1.
Shielding is an AC effect and, therefore, shields may be alternately tied to VDD. There are 2 types of effects that this shielding helps fix. In the first, these grounded signals help prevent unwanted capacitive coupling from the clock to adjacent signals (or visa versa). In the second, these shields provide a low impedance return path for the currents induced inductively by the changing current on the clocks. Without these shields, those currents find their way back through adjacent signals and the chip substrate which can cause unwanted timing variation. Because the shielding introduces many millimeters of minimum space parallel routing, this technique typically decreases yield due to increased sensitivity to defects. Defects in the die are detected by fails at test. With the clock shielding structure shown in FIG. 1, a defect which shorts a clock wire to a shield, will cause a fail at test, and the die or module would be scrapped. However, with conventional structures, the root cause of the test fail will be unknown. Valuable information relating to the root cause of the test fail, such as the defect density, defect location or process levels involved, is not directly provided from the conventional test results. At manufacturing test, this defect will typically fail the quiescent current (IDDq) test or a pattern test (AVP/LSSD/etc.). Chips with this defect will be grouped with other chips that fail these test categories. While logic diagnostics, IDDq diagnostics, physical fault isolation, or tester base diagnostics techniques may be used to determine the location of the defect and root cause, determining defect location and root cause for a large number of manufactured chips can be time and resource intensive. The invention described below addresses these concerns.